List of Experiments / Activities
- 0L:0T:2P 1 Credits
- SUGGESTIVE LIST OF EXPERIMENTS:
- 1Simulate all gates using VHDL.
- 2Design and simulate Half adder and Full adder using VHDL.
- 3Design and simulate Multiplexer and Demultiplexer using VHDL.
- 4Design and simulate Encoder and Decoder using VHDL.
- 5Simulate Flip flops using VHDL.
- 6Implement shift register using VHDL.
- 7FPGA implementation of Flip flops.
- 8FPGA implementation of shift register.
- 9Design and implement 4-bit Synchronous and Asynchronous Counters on FPGA
- 10Implement Binary Multiplier using FPGA
Course Outcomes (COs)
After completion of the course student will be able to:
- CO1Design and simulate basic logic gates and arithmetic circuits using VHDL.
- CO2Design and simulate multiplexers, encoders, and decoders using VHDL.
- CO3Implement sequential logic circuits such as flip-flops and shift registers using VHDL.
- CO4Implement and test sequential and arithmetic circuits on FPGA hardware.
- CO5Demonstrate the ability to integrate and debug VHDL code in FPGA-based digital design workflows. Page
Official AKTU syllabus
This subject is on page 29, 30 of the original AKTU PDF.