VLSI Circuit Testing and Testability

Fault modelling, fault detection, redundancy, equivalence, fault location, fault dominance. Stuck at faults, bridging faults, stuck open faults, Transient faults, Permanent faults.

Testing and Testability of Combinational Circuits Test generation basics, test generation algorithms, path sensitization, Boolean difference, D-algorithm, PODEM, Testable combinational logic circuit design.

Testing and Testability of Sequential Circuits Testing of sequential circuits as iterative combinational circuits, State table verification, Test generation based on circuit structure, Design of testable sequential circuits, Ad Hoc design rules, Scan path technique (scan design), Partial scan, Boundary scan

Memory, Delay, Fault AND IDDQ Testing Testable memory design, RAM fault models, test algorithms for RAMs, Delay faults, Delay test, IDDQ testing, limitations of IDDQ Testing

controllability and observability, Random test generation, transition count testing, signature analysis, syndrome testable design, RMC, Level sensitive scans design, BIST: LSSD on-chip self-test, BILBO, BIDCO.