Low Power VLSI Design

Sources of power dissipation – Physics of power dissipation in MOSFET devices: The MIS structure, long channel MOSFET, Submicron MOSFET, gate induced drain leakage– Power dissipation in CMOS: short circuit dissipation, dynamic dissipation, load capacitance– Low power VLSI design: Limits – principles of low power design.

Transistor and Gate Sizing: Sizing an Inverter Chain, Transistor and Gate Sizing for Dynamic Power Reduction, Transistor Sizing for Leakage Power Reduction - Network Restructuring and Reorganization: Transistor Network Restructuring, Transistor Network Partitioning and Reorganization - Special Latches and Flip-flops: Self-gating Flip-flop, Varieties of Boolean Functions, Adjustable Device Threshold Voltage.

Behavioral Level Transforms, Logic Level Optimization for Low power, Circuit Level Optimization

Organization of a static RAM, MOS Static RAM Memory cell, Banked organization of SRAMs, Reducing voltage swings on bit lines, Reducing power in write driver circuits, Reducing power in sense amplifier circuits, method for achieving low core voltages from a single supply.

Circuit Design style, Leakage current in deep submicrometer transistors, Deep submicrometer device design issues, Low voltage circuit design techniques, Designing deep submicrometer ICs with elevated intrinsic leakage, multiple supply voltages.