Digital Integrated Circuit Design

Introduction to ASIC and FPGA Design Flow: RTL-to-GDSII flow, Role of synthesis in digital design Basics of Hardware Description Languages (HDLs): System Verilog vs. VHDL for synthesis, RTL coding guidelinesandstyles for efficient synthesis. Introduction to Pre-Synthesis Analysis and RTL Quality Checks using Lint, CDC, RDC, and Formal Verification technologies such as Siemens Questa SFV, Cadence JasperGold and Verisium, Synopsys VC Formal and SpyGlass, etc.

Definition and purpose of synthesis, technology independent vs. technology-dependent optimizations, synthesis tools overview (Siemens EDA – Precision RTL/Aprisa, Cadence – Genus/Innovus, Synopsys – Design Compiler/IC Compiler II), etc.

Fundamentals of Timing Analysis: Setup time, hold time, propagation delay, Clock period, clock skew, and clock jitter.

Types of Timing Paths in a Digital Circuit: Data path, clock path, asynchronous paths, Critical path analysis. Timing Models and STA Basics: Transition time, cell delay, net delay, Wire-load models, parasitic extraction.

Introduction to Static Timing Analysis (STA), Introduction to Gate-Level Simulation (GLS) and verification, understanding Standard Delay Format (SDF), GLS using Siemens QuestaSim, Cadence Xcelium, or Synopsys VCS, Functional Verification using Siemens Questa Formal/Questa SFV, Cadence JasperGold, or Synopsys VC Formal, Pre- and Post-Synthesis Analysis, and Introduction to Power Analysis using Siemens PowerPro, Cadence Joules, or Synopsys PrimePower. Note: As mentioned above any ONE of the three EDA tools may be made use of depending upon the availability. The questions asked in exam will not be from any specific EDA tool and will be of generic nature.