Unit 1
Review of Logic Design Fundamentals: Combinational logic, hazards in combinational networks, Mealy and Moore sequential circuit design, sequential circuit timing, setup and hold times.
B.Tech Electrical Engineering · Sem 6 (Departmental Elective-III) · B.Tech Electrical & Electronics Engineering · Sem 6 (Departmental Elective-III)
Pre-requisites: Digital Electronics and Circuits and Basic course on Microprocessors
Review of Logic Design Fundamentals: Combinational logic, hazards in combinational networks, Mealy and Moore sequential circuit design, sequential circuit timing, setup and hold times.
Introduction, VHDL terms, code structure, data types, operators and attributes, concurrent and sequential code, variables and signals, subprograms and procedures, packages and libraries, pre-defined attributes. VHDL Description of Combinational Circuits: Multiplexers, decoders, encoders, code converters. VHDL Description of Sequential Circuits: Flip-flops, registers, counters, clock synchronization.
Design of Programmable Logic Devices: Read-only memories, programmable logic arrays, programmable array logics, Design of Circuits with Arithmetic Operations: Serial adder, binary multiplier, multiplication of signed numbers, binary divider Design of Memories: VHDL models for memories and buses, simplified bus model, interfacing memory to a microprocessor bus.
Design with Programmable Gate Arrays: Introduction of FPGAs, designing with FPGAs and CPLDs. Hardware Testing and Design: Testing combinational logic, testing sequential logic, scan testing.
Case Study: Design of UART, design of microcontroller CPU, top-level CPU design, sample
After completion of the course student will be able to:
This subject is on page 50 of the original AKTU PDF.