Advance Digital Design using Verilog

Introduction to Mixed Logic, Logic Representation and Minimization with cost, Multiple output minimization, Entered Variable K- Map including don’t care handling, XOR Pattern Handling.

Combinational Circuit Design, Multiplexers, Decoders, Encoders, Code Comparators, Adders, Subtractors, Multipliers, Introduction to Verilog, Behavioral and Structural specification of logic circuits, Boolean function implementation using Verilog, Timing Analysis, Hazard Detection and Elimination

Synchronous Sequential Circuits Design, Mapping Algorithm, Synchronous State Machines, ASM Charts, Asynchronous Sequential Circuit Design, Races, Multi-level minimization and optimization.

Factoring, Decomposition, BDD, Ordered BDD, LPDD, Fault Detection and Analysis in combinational and sequential systems, Path Sensitization method, Boolean Difference Method, Initial State Method.

Study of programmable logic families, PLD, CPLD, FPGA, ASIC, PLA, Architectures, Design of Combinational and sequential circuits using CPLD and FPGA, Design Examples.