BEC653B

CAD (Computer-Aided Design) for Electronics Lab

L-T-P0-0-2 Credits1 Session2025-26 TypeLab / Practical
Appears in 2 semesters · 2 branches

B.Tech ECE (Advanced Communication Technology) · Sem 6 (Elective Lab) · B.Tech Electronics Engineering (VLSI Design & Technology) · Sem 6 (Elective Lab)

List of Experiments / Activities

  1. CAD (COMPUTER-AIDED DESIGN) FOR ELECTRONICS LAB 0L:0T:2P 1 Credit
  2. Part A
  3. SUGGESTIVE LIST OF EXPERIMENTS:
  4. PSPICE Experiments:
  5. 1(a) Transient Analysis of BJT inverter using step input. (b) DC Analysis (VTC) of BJT inverter
  6. 2(a) Transient Analysis of NMOS inverter using step input. (b) Transient Analysis of NMOS inverter using pulse input. (c) DC Analysis (VTC) of NMOS inverter.
  7. 3(a) Analysis of CMOS inverter using step input. (b) Transient Analysis of CMOS inverter using step input with parameters. (c) Transient Analysis of CMOS inverter using pulse input. (d) Transient Analysis of CMOS inverter using pulse input with parameters. (e) DC Analysis (VTC) of CMOS inverter with and without parameters.
  8. 4Transient & DC Analysis of NAND Gate using CMOS inverter.
  9. 5Transient Analysis of NOR Gate inverter and implementation of XOR gate using NOR gate
  10. 6To design and perform transient analysis of D latch using CMOS inverter.
  11. 7To design and perform the transient analysis of SR latch circuit using CMOS inverter.
  12. 8To design and perform the transient analysis of CMOS transmission gate.
  13. 9Analysis of frequency response of Common Source amplifiers.
  14. 10Analysis of frequency response of Source Follower amplifiers
  15. Part B : HDL (using VHDL program module & verilog Module) VHDL PROGRAMS
  16. 1Design and Simulation of Full Adder using VHDL program module
  17. 2Design and Simulation of 4x1 MUX using VHDL program module
  18. 3Design and Simulation of BCD to Excess-3 code using VHDL program module
  19. 4Design and Simulation of 3 to 8 decoder using VHDL program module
  20. 5Design and Simulation of JK Flip-flop using VHDL program module
  21. 6Design and Simulation of CMOS Inverter using verilog Module
Course Outcomes (COs)4 outcomes

After completion of the course student will be able to:

  1. CO1Design and analyze the performance of different type of inverters.
  2. CO2Design and analyze the performance of the basic logic gates using CMOS inverter circuit.
  3. CO3Design and analyze the performance of the memory based digital circuits using CMOS inverter circuit.
  4. CO4Analyze the performance of the different configuration of MOS amplifier circuits.

Official AKTU syllabus

This subject is on page 32 of the original AKTU PDF.

Official AKTU syllabus PDF ↗