VLSI Design Flow: RTL to GDS

Fundamentals of VLSI Design Flow and HDL Basic concept of Integrated Circuits, Moore’s law, Scales of Integration, Introduction to ASIC and SoC design, VLSI Design flow, FPGA Design Flow, Technology nodes, GDSII file format definition, PDK definition, Introduction to EDA tools used in front-end and back-end design. VLSI Design Styles Basics of Hardware Description Languages (HDLs): Verilog HDL fundamentals, modeling styles – Dataflow, Behavioral and Structural modeling. Module definition, ports, data types and operators in verilog.

RTL Design and Functional Verification Blocking vs Non-blocking assignments, Always blocks-combinational & sequential modeling, Control blocks: if-else, case and loops. RTL implementation of combinational and sequential circuits. FSM design (Moore & Mealy). Functional simulation and test benches development. Introduction to simulation tools (e.g., Xcelium) and waveform analysis.

Logic Synthesis and Static Timing Analysis Logic synthesis flow: RTL to gate-level netlist. Technology mapping and synthesis constraints (introduction to SDC). Inputs and outputs of synthesis, Gate-level netlist generation and analysis. Overview of synthesis optimization (timing, area and power – introductory). Synthesis tools overview. Static Timing Analysis (STA): Propagation delay, clock skew, and clock jitter. Setup and hold check. Timing paths, slacks and timing reports.

Introduction to Physical Design Overview of Physical Design flow. Floorplanning concepts and partitioning (basic). Placement of standard cells and macros (overview). Clock Tree Synthesis (CTS) – concept and objectives. Routing – global and detailed routing (introductory). Power planning basics (power rings, power stripes). Congestion analysis (basic understanding).

Physical Verification and Signoff Design Rule Checking (DRC) – purpose and methodology. Layout vs Schematic (LVS), Parasitic extraction (RC extraction overview), Introduction to Signal integrity and IR drop concepts, Tape-out procedure and GDSII generation.