ASIC Design and Verification

ASIC Design Flow and System Verilog Fundamentals Overview of ASIC design flow, Role of RTL and Verification in ASIC design. SystemVerilog overview and evolution from Verilog. Data Types: logic, bit, reg, wire, Constants, Net Type, Arrays: static, dynamic, associative, queues, Enumerated types, Typedef and packages, String, Operators and expressions. Procedural statements and Routines - Procedural Statements, Specialized constructs: always_comb, always_ff, always_latch. Tasks, Functions, and Void Functions, Routine arguments – Returning from a routine.

Combinational Circuit Modeling using SystemVerilog Continuous assignments. Sensitivity lists and always_comb., Blocking assignment, Modeling and verification of-Multiplexer, Encoder / Decoder, Adder / Subtractor, Comparator, Parameterized combinational modules

Sequential Circuit Modeling using SystemVerilog always_ff construct, non-blocking assignment, Modeling and verification of- Flip-flops, Counters (Up/Down, Mod-N), Shift registers, FSM design (Moore & Mealy). Clock and reset strategies (synchronous/asynchronous).

Verification Fundamentals Need for verification, Testing Vs Verification, Separation of Testbench and Design, Testbench architecture. Interface Construct, Stimulus Timing, Module interactions. Direct Testing. Self-checking testbench. Scoreboard concept. System Verilog Assertions, Procedural and Concurrent Assertions.

Digital Design using FPGA FPGA Design flow, Applications of FPGA, FPGA Architecture, Introduction to FPGA development environments (Vivado Tool), FPGA implementation of combinational circuits: logic gates, adder, subtractor, decoder, multiplexer. FPGA implementation of sequential circuits: Flip flops and counter with & without inclusion of constraint file.