UNIQUE SERIES AKTU Syllabus
BCS302BCS302H

Computer Organization and Architecture

L-T-P3-1-0 Credits4 Session2023-24 TypeTheory
Appears in 14 semesters · 14 branches

B.Tech Computer Science & Engineering · Sem 3 (Core, code BCS302) · B.Tech Information Technology · Sem 3 (Core, code BCS302) · B.Tech Artificial Intelligence & Machine Learning · Sem 3 (Core, code BCS302) · B.Tech Artificial Intelligence & Data Science · Sem 3 (Core, code BCS302) · B.Tech CSE (Artificial Intelligence) · Sem 3 (Core, code BCS302) · B.Tech CSE (AI & ML) · Sem 3 (Core, code BCS302) · B.Tech CSE (Data Science) · Sem 3 (Core, code BCS302) · B.Tech CSE (Cyber Security) · Sem 3 (Core, code BCS302) · B.Tech CSE (Internet of Things) · Sem 3 (Core, code BCS302) · B.Tech Computer Science & Design · Sem 3 (Core, code BCS302) · B.Tech Computer Science (Hindi) · Sem 3 (Core, code BCS302H) · B.Tech Computer Science & Business Systems · Sem 3 (Core, code BCS302) · B.Tech Cyber Security · Sem 3 (Core, code BCS302) · B.Tech Data Science · Sem 3 (Core, code BCS302)

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Syllabus

5 units · 40 lecture hours
Unit1

Unit 1: Introduction

8 hrs

Functional units of digital system and their interconnections, buses, bus architecture, types of buses and bus arbitration. Register, bus and memory transfer. Processor organization, general registers organization, stack organization and addressing modes.

Unit2

Unit 2: Arithmetic and logic unit

8 hrs

Look ahead carries adders. Multiplication: Signed operand multiplication, Booths algorithm and array multiplier. Division and logic operations. Floating point arithmetic operation, Arithmetic & logic unit design. IEEE Standard for Floating Point Numbers

Unit3

Unit 3: Control Unit

8 hrs

Instruction types, formats, instruction cycles and sub cycles (fetch and execute etc), micro operations, execution of a complete instruction. Program Control, Reduced Instruction Set Computer, Pipelining. Hardwire and micro programmed control: micro programme sequencing, concept of horizontal and vertical microprogramming.

Unit4

Unit 4: Memory

8 hrs

Basic concept and hierarchy, semiconductor RAM memories, 2D & 2 1/2D memory organization. ROM memories. Cache memories: concept and design issues & performance, address mapping and replacement Auxiliary memories: magnetic disk, magnetic tape and optical disks Virtual memory: concept implementation.

Unit5

Unit 5: Input / Output

8 hrs

Peripheral devices, I/O interface, I/O ports, Interrupts: interrupt hardware, types of interrupts and exceptions. Modes of Data Transfer: Programmed I/O, interrupt initiated I/O and Direct Memory Access., I/O channels and processors. Serial Communication: Synchronous & asynchronous communication, standard communication interfaces.

Course Outcomes (COs)5 outcomes

After completion of the course student will be able to:

  1. CO1Study of the basic structure and operation of a digital computer system.K1, K2
  2. CO2Analysis of the design of arithmetic & logic unit and understanding of the fixed point and floating-point arithmetic operations.K2, K4
  3. CO3Implementation of control unit techniques and the concept of PipeliningK3
  4. CO4Understanding the hierarchical memory system, cache memories and virtual memoryK2
  5. CO5Understanding the different ways of communicating with I/O devices and standard I/O interfacesK2, K4

Note: The B.Tech Cyber Security and Data Science syllabus PDF (2nd year, effective from 2025-26) prints new course outcomes for this subject: CO1: Explain the organization of a digital computer system, processor architecture, register organization, buses, memory transfer, and addressing modes (K2); CO2: Analyze arithmetic and logic unit (ALU) operations (K4); CO3: Analyze the design and operation of hardwired and microprogrammed control units, instruction execution cycles, and pipelining techniques for processor performance enhancement (K4); CO4: Evaluate the performance of memory hierarchy, cache memory, virtual memory, and secondary storage techniques for efficient memory management (K5); CO5: Evaluate input/output organization, interrupt handling, data transfer techniques, and serial communication interfaces for effective interaction between the processor and peripheral devices (K5).

Text books

  1. Computer System Architecture - M. Mano
  2. Carl Hamacher, Zvonko Vranesic, Safwat Zaky Computer Organization, McGraw-Hill, Fifth Edition, Reprint 2012
  3. John P. Hayes, Computer Architecture and Organization, Tata McGraw Hill, Third Edition, 1998. Reference books
  4. William Stallings, Computer Organization and Architecture-Designing for Performance, Pearson Education, Seventh edition, 2006.
  5. Behrooz Parahami, “Computer Architecture”, Oxford University Press, Eighth Impression, 2011.
  6. David A. Patterson and John L. Hennessy, “Computer Architecture-A Quantitative Approach”, Elsevier, a division of reed India Private Limited, Fifth edition, 2012
  7. Structured Computer Organization, Tannenbaum(PHI)

Official AKTU syllabus

This subject is on page 6 of the original AKTU PDF.

Official AKTU syllabus PDF ↗